Multilayer wiring boards of an all-layer build-up structure are components for electronic devices that have been developed for the purpose of forming complicated high-density electronic circuits and mounting various electronic components at high density thereon. Such multilayer wiring boards of an all-layer build-up structure have a structure in which a plurality of wiring layers constituted by copper wiring elements and a resin and a plurality of resin base material layers constituted by a resin and fiber bundles are alternately layered, and are used in various digital devices and mobile devices.
First, a typical multilayer wiring board of an all-layer build-up structure will be described.
FIG. 9 shows the basic configuration of such a multilayer wiring board. In a multilayer wiring board of an all-layer build-up structure (hereinafter referred to as a “board”) 100a, n (n: an integer equal to or larger than 3) wiring layers (C1 to Cn) and (n−1) resin base material layers (B1 to B(n−1)) are laminated in an alternately layered manner. In the following description, the wiring layers and the resin base material layers are referred to collectively as “wiring layers C” and “resin base material layers B”, respectively, as occasion demands.
The wiring layers C are constituted by copper wiring elements 101 and an insulating resin 103. The resin base material layers B are constituted by a fiber bundle 102 in fabric form and the insulating resin 103 with which the fiber bundle 102 is impregnated. FIG. 9 schematically shows a state in which the fiber bundle 102 is impregnated with the resin 103 as the resin base material layer B. The layers are similarly shown also in the subsequent figures.
As the fiber bundle 102, glass fibers or aramid fibers are ordinarily used. As the insulating resin 103, a thermosetting resin such as an epoxy resin, a phenol resin, polyimide or a BT resin is used.
Typically, the wiring layers C and the resin base material layers B are formed by alternately layering fiber bundles impregnated with an insulating resin and copper foils with wiring patterns formed thereon, and by curing the resin by application of pressure and heat in this state. The resin 103 constituting the wiring layers C is formed by causing a part of the resin with the fiber bundles impregnated to enter gaps between the wiring patterns, at the time of application of pressure and heat.
Although not shown, the wiring layers C are electrically connected via via-holes or through holes formed through the resin base material layers B. The above-described configuration of the multilayer wiring board having an all-layer build-up structure is defined in detail in the following document: “JPCA Standard Build-up Printed Wiring Boards (Terms) (Test Methods)”, Edited by Noritaka Nagashima, Japan Electronics Packaging and Circuits Association (see structural examples 3 and 4 on page 2).
The resin base material layers B are divided into a base layer 104 as a central layer in the multilayer structure and build-up layers 105 laminated above and below the base layer 104 in a laminating press process in the manufacture of the board. Resin base materials constituting the base layer 104 and the build-up layers 105 may be the same or different. As a resin base material for each of the build-up layers 105, a single material is used in which the fiber bundle content is constant.
In a reflow soldering process, the board 100a is placed on a reflow belt or reflow pallet, with electronic components temporarily fixed on its front and rear mounting faces, and the temperature of the board is raised from room temperature to 220° C. or more to perform soldering and then lowered to room temperature. In the board 100a at this point, a difference in the amount of thermal expansion occurs between the wiring layers because the proportions of copper remaining therein (the proportions of areas occupied by the copper wiring elements in the entire areas of the wiring layers C) differ from each other. Warpage occurs due to this difference.
The mechanism how warpage of the board occurs will be concretely described with reference to FIG. 10.
A board 100f shown in FIG. 10 has six wiring layers C1 to C6 in this order from the top down and five resin base material layers B1 to B5 interposed between the wiring layers C in this order from the top down. (Each of the resin base material layers B1 and B2 is the build-up layer 105, the resin base material layer B3 is the base layer 104, and each of the resin base material layers B4 and B5 is the build-up layer 105.) The proportions of copper remaining in the wiring layers are 32%, 28%, 37%, 46%, 52% and 54% in the order from the wiring layer C1. In this case, the average of the proportions of copper remaining in the layers (C4 to C6) below the base layer 104 is larger than the average of the proportions of copper remaining in the layers (C1 to C3) above the base layer 104 (the resin base material layer B3).
When the copper wiring element 101 and the resin 103 constituting the wiring layers C are compared, the coefficient of linear expansion of the resin 103 is larger than that of the copper wiring element 101. Therefore, the wiring layers with a higher proportion of copper remaining have a smaller amount of thermal expansion under a temperature load. Thus, in the board 100f shown in FIG. 10, the amount of thermal expansion of the layers above the base layer 104 is larger because the proportion of copper remaining is lower (the amount of the resin is larger), and the amount of thermal expansion of the layers below the base layer is smaller because the proportion of copper remaining is higher (the amount of the resin is smaller). Accordingly, when a temperature load is applied, the board is warped upward convexly.
If the horizontal direction of the board 100f shown in FIG. 10 is defined as a weft direction, and if a direction perpendicular to the plane of projection in FIG. 10 is defined as a warp direction, the board warps in such a manner that the amount of warpage in the weft direction and the amount of warpage in the warp direction differ from each other in ordinary cases, as shown in FIG. 12, because pieces of wiring of an electronic circuit are non-uniformly disposed on the multilayer wiring board. This phenomenon, in which the board warps in saddle form, is called “saddle warpage”.
If electronic components are mounted in a state where warpage of the board exists in the reflow soldering process, the reliability of connections between the electronic components and the board is considerably reduced, which is a significant factor that deteriorates the quality of an electronic circuit incorporating the multilayer wiring board.
In order to prevent warpage of the board in the reflow soldering process, the countermeasure shown in Japanese Laid-Open Patent Publication No. 2000-151035 is conventionally adopted. That is to say, as shown in FIG. 9, in order to minimize differences in the amount of thermal expansion derived from the different proportions of copper remaining in the wiring layers C, dummy patterns 108 are formed in the wiring layers C aside from the essential copper wiring elements 101 constituting the electronic circuit, thereby making the proportions of copper remaining in the wiring layers C as uniform as possible.
In a board for a small electronic device requiring high-density mounting of an electronic circuit, however, spaces sufficient for the provision of dummy patterns 108 in wiring layers cannot be secured and it is difficult to reduce warpage of the board. Moreover, there is presently no technique effective in reducing the amount of warpage only in one direction to suppress the above-described saddle warpage.
It is therefore an object of the present invention to provide a multilayer wiring board capable of reducing saddle warpage even if there is no space for providing dummy patterns in wiring layers.